In the semiconductor industry, the minimum feature sizes of microelectronic devices are well into the deep sub-micron regime to meet the demand for faster, and lower power semiconductor devices. The downscaling of complimentary metal-oxide-semiconductor (CMOS) devices imposes scaling constraints on the gate dielectric material. The thickness of the conventional SiO2 gate dielectric is approaching its physical limits. The most advanced devices are using nitrided SiO2 gate dielectrics approaching equivalent oxide thickness (EOT) of about 1 nanometer (nm) or less where the leakage current density can be as much as 1 mA/cm2. To improve device reliability and reduce electrical leakage from the gate dielectric to the transistor channel during operation of the device, semiconductor transistor technology is planning on using high dielectric constant (high-k) gate dielectric materials that allow increased physical thickness of the gate dielectric layer while maintaining a low equivalent oxide thickness (EOT). Equivalent oxide thickness is defined as the thickness of SiO2 that would produce the same capacitance voltage curve as that obtained from an alternate dielectric material.
Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. High-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2, HfSiO, ZrSiO, etc) rather than grown on the surface of the substrate as is the case for SiO2. High-k materials may incorporate a metal oxide layer or a metal silicate layer, e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO (k˜5–20), and HfO2 (k˜25).
Integration of high-k materials into gate stacks can require a dielectric interfacial layer at the surface of the Si substrate to preserve interface state characteristics and form an interface with good electrical properties. However, the presence of an oxide interfacial layer lowers the overall dielectric constant of the stack and, therefore, the oxide interfacial layer may need to be thin. The quality of the interfacial oxide dielectric layer can affect device performance, as the oxide layer is intimately connected to the channel of the transistor.
As-deposited high-k gate dielectric layers commonly contain point defects, vacancies or impurities that are incorporated into the high-k layers during the deposition process. These defects can be the source of high leakage currents in the dielectric layer and may eventually be responsible for premature failure of the dielectric layer and the microelectronic device. Annealing procedures have been developed to decrease these point defects, however, high temperatures are usually required for maximum improvement, which can increase the thickness of the interfacial oxide layer.